1. Field of the Invention
The present invention relates to a semiconductor device which in particular is provided with a capacitive element having a MIM (Metal-Insulator-Metal) structure. Moreover, the present invention also relates to a method of manufacturing such semiconductor device.
2. Background Information
A common LSI (Large Scale integration) semiconductor is composed of various basic elements integrated to high density. The basic elements incorporated in a LSI semiconductor can be classified into two prominent categories, which are active elements and inactive elements.
One typical active element would be a transistor. There are several types of transistors such as a bipolar junction transistor (BJT), a junction field effect transistor (JFET), a metal oxide semiconductor field effect transistor (MOSFET), and so forth. Besides silicon (Si), which is commonly used as a material for forming a transistor, it is also possible to use a compound semiconductor such as gallium arsenide (GaAs), indium phosphide (InP) or the like.
On the other hand, a typical inactive element would be a resistive element or a capacitive element. Generally, such inactive element is formed using various conductive films and insulation films formed in the processes of forming a transistor. For instance, a capacitive element is usually formed having two layers of polysilicon electrodes and an interlayer of a silicon nitride film between the two layers of polysilicon electrodes.
In recent years, the signal processing speed of a LSI semiconductor has been improving rapidly with the increase in speed in transistor operations. On the other hand, due to the increase in communications traffic, it will be necessary to further increase the speed of LSI operations. Under such circumstances, it will be necessary to have a capacitive element with a high responsivity.
Generally, a delay of an electric signal is generated due to the coupling of a resistance (R) and a capacitance (C). Quantitatively, the amount of delay in a signal is determined based on a time constant that can be obtained by CXR. With respect to the capacitance (C) of a capacitive element, the capacitive element itself is an unchangable function. Accordingly, in order to prevent unnecessary signal delay, it is necessary to reduce the resistance (R) of the capacitive element. However, because a conventional capacitive element uses polysilicon, for instance, as its electrode, the parasitic resistance tends to become large, and thereby, an unnecessary time constant has to be added.
In order to cope with such problems, in recent years, a capacitive element having an MIM structure using a metal wiring as an electrode, such as the one disclosed in Washio, et al., “A 0.2-μm 180-GHz-fmax 6.7-ps-ECL SOI/HRS Self-Aligned SEG SiGe HBT/CMOS Technology for Microwave and High-Speed Digital Applications”, IEEE International Electron Devices Meeting (IEDM), pp. 741-742, 2000 (hereinafter referred to as Non-Patent Reference 1), has come to be widely used. In the following, conventional technology relating to such capacitive element will be referred to as Prior Art Technology 1.
Now, a method of manufacturing a capacitive element having an MIM structure according to Prior Art Technology 1 will be described. Normally, in a typical manufacturing method, formation of various component elements, formation of insulation films after the component elements are formed, formation of contacts for connecting the component elements with wirings, etc. are supposed to be conducted in advance. In the following description, only processes for forming the MIM structure will be briefly described, and the other processes with respect to the above formation of component elements etc., for instance, will be omitted.
In this conventional manufacturing method, first, a semiconductor wafer (hereinafter to be referred to simply as a wafer) having an insulation film formed on a surface thereof is prepared, and a metal film is formed on the entire upper surface of this wafer. Then the metal film is processed using known photolithographic and etching processes. By these processes, a first metal pattern including a lower electrode of the capacitive element and other metal patterns is formed.
Next, an insulator is deposited over the entire surface of the wafer to form an insulation film, after which a surface of the insulation film is planarized by CMP (Chemical and Mechanical Polishing) to form an interlayer insulation film in which the thickness from the surface of the first metal pattern is about 6000 Å (angstrom), for instance.
Next, by etching the interlayer insulation film on the lower electrode in the first metal pattern, an opening having a diameter slightly smaller than that of the lower electrode is formed. Then, using a plasma CVD (Chemical Vapor Deposition) method, an HDP (High-Density Plasma) film, which is an insulation film, is formed on the entire surface of the wafer, i.e., on the interlayer insulation film and inside the opening, with a thickness of about 2000 Å.
Next, a contact hole with an opening diameter about 0.5 μm is formed over a region where the capacitive element is not formed, and tungsten (W) is deposited over the entire surface of the wafer to the thickness of about 8000 Å, in order to form contact plugs. During this time, the inside of the contact hole will be filled with tungsten (W) while the inside of the opening covered with the HDP film will also be filled up with tungsten.
Next, by etching back the entire surface of the wafer, the tungsten film over the interlayer insulation film is removed while leaving the tungsten inside the contact hole. Here, the tungsten remaining inside the contact hole functions as the contact plug for electrically connecting the upper and lower layers sandwiching the interlayer insulation film in between.
Then, a metal film is formed over the entire surface of the wafer, after which the metal film is processed using known photolithographic and etching processes to form a second metal pattern having an upper electrode of the capacitive element and other metal patterns. By these processes, a capacitive element having an MIM structure can be formed.
However, normally, the diameter of the opening formed for the capacitive element is considerably larger than the diameter of the contact hole. Therefore, in the process of removing the tungsten film over the interlayer insulation film, a portion of the tungsten will remain on the inner surface of the opening in the form of sidewalls. Such residual tungsten film may be a factor leading to problems such as the peeling off of a film formed on the tungsten film, and the like. As a result, this may cause other problems, such as defects in manufacturing processes and a decrease in a yield ratio.
One conventional method that resolves such problems is introduced in Japanese Laid-Open Patent Application No. 2003-31691 (hereinafter referred to as Patent Reference 1), for instance. In Patent Reference 1, the opening normally used in the capacitive element is replaced with multiple contact holes in order to prevent unnecessary tungsten film from remaining in the form of sidewalls. In the following, this technology will be referred to as Prior Art Technology 2.
Furthermore, another conventional method is introduced in Japanese Laid-Open Patent Application No. 2003-133414 (hereinafter referred to as Patent Reference 2), for instance. In Patent Reference 2, the opening normally used in the capacitive element is replaced with a liner opening trench having the same width as the diameter of the contact hole in order to prevent unnecessary tungsten film from remaining in the form of sidewalls. In the following, this technology will be referred to as Prior Art Technology 3.
However, according to Prior Art Technology 2 or 3, since multiple contact holes or a linear opening trench is used for the opening over the lower electrode, an area of the upper electrode adjacent to the lower electrode has to become smaller, which results in the reduction of the capacitive density of the capacitive element. Therefore, in order to obtain a desired capacitance, it is necessary to enlarge an area between the electrodes of the capacitive element, and this leads to a problem of increasing size of a semiconductor device.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved semiconductor device and an improved method of manufacturing a semiconductor device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.